Junhyuk Choi, Ilkwon Byun, Juwon Hong, Dongmoon Min, Junpyo Kim, Jungmin Cho, Hyeonseong Jeong, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, “SuperCore: An Ultra-Fast Superconducting Processor For Cryogenic Applications,” the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.1532-1547, Nov. 2024.

Satoshi Kawakami, Yusuke Ohtusbo, Koji Inoue, and Masamitsu Tanaka, “Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-2, Mar. 2024.

Yueyue He, Koji Inoue, and Jiageng Chen, “CFChain: A crowdfunding platform that supports identity authentication, privacy protection, and efficient audit,” The 23rd International Conference on Algorithms and Architectures for Parallel Processing, Oct. 2023.

Dongmoon Min, Junpyo Kim, Junhyuk Choi, Ilkwon Byun, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, “QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy,” ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.1-16, June 2023.

Wang LIAO, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, and Yuuki Tokunaga, “WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code,” 28th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.209-215, Jan. 2023.

Yuan Wang, Hidetomo Shibamura, Kuan Yi Ng, and Koji Inoue, “Implementation of Edge-cloud Cooperative CNN Inference on an IoT Platform,” The 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.337-344, Dec. 2022.

Eito Sato, Koji Inoue, and Satoshi Kawakami, “Design and Analysis of a Nano-photonic Processing Unit for Low-Latency Recurrent Neural Network Applications,” The 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.321-329, Dec. 2022.

Takumi Inaba, Takatsugu Ono, Koji Inoue, and Satoshi Kawakami, “A Hybrid Opto-Electrical Floating-point Multiplier,” The 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.313-320, Dec. 2022.

Ikki Nagaoka, Ryota Kashima, Tomoki Nakao, Masamitsu Tanaka, Taro Yamashita, Koji Inoue, and Akira Fujimaki, “A 57.2GHz 11.2mW 8-Bit General Purpose Superconductor Microprocessor with Dual-Clocking Scheme,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022.

Satoshi Matsushita, Teruo Tanimoto, Satoshi Kawakami, Takatsugu Ono, and Koji Inoue, “An Edge Autonomous Lamp Control with Camera Feedback,” IEEE 8th World Forum on Internet of Things, Oct. 2022.

Yasunari Suzuki, Takanori Sugiyama, Tomochika Arai, Wang Liao, Koji Inoue, and Teruo Tanimoto, “Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays,” the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.1110-1125, Oct. 2022.

Tomohiro Fujii and Masao Hirokawa, “On Performance of Concealing-Restoring System for Analog Signals on Physical Layer,” International Conference on Electrical, Computer and Energy Technologies (ICECET), July 2022.

Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim, “XQsim: Modeling Cross-Technology Control Processors for 10+K Qubit Quantum Computers,” ACM/IEEE International Symposium on Computer Architecture (ISCA), pp. 366-382, June 2022.

Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, and Koji Inoue, “Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device,” International Symposium on Circuits & Systems (ISCAS), pp.1-5, May 2022.

Masao Hirokawa, “On Accuracy of Restoration of Concealing-Restoring System for Physical Layer,” International Conference on Electrical, Computer and Energy Technologies (ICECET), Dec. 2021.

Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, “SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices,“ 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.58–72, Oct. 2020.

Tomohiro Fujii, Masao Hirokawa, “A Data Concealing Technique with Random Noise Disturbance and A Restoring Technique for the ConcealedData by Stochastic Process Estimation,” The International Symposium on Mathematics, Quantum Theory, and Cryptography, Mathematics for Industry, Vol.33, pp.103-124, Oct. 2020.

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, and Koji Inoue, “How many trials do we need for reliable NISQ computing?,” In The First International Workshop on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA) in conjunction with the ISVLSI, July 2020.

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, and Koji Inoue, “Practical error modeling toward realistic NISQ simulation,” In The First International Workshop on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA) in conjunction with the ISVLSI, July 2020.

Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue, “32 GHz 6.5 mW Gate-Level-Pipelined 4-bit Processor using Superconductor Single-Flux-Quantum Logic,” 2020 Symposia on VLSI Technology and Circuits, June 2020.

Keitaro Oka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koji Inoue, “Enhancing a manycore-oriented compressed cache for GPGPU,” International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2020), pp.22-31, Jan. 2020.

Susumu Mashimo, Ryota Shioya, Koji Inoue, “Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core,” International Conference on High Performance Computing in Asia-Pacific Region (HPC Asia 2020), pp.207-216, Jan. 2020.

Susumu Mashimo, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima, Koji Inoue, Ryota Shioya, “An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor,” IEEE International Conference on Field Programmable Technology (FPT), pp.63-71, Dec. 2019.

Giorgis Georgakoudis, Nikhil Jain, Takatsugu Ono, Koji Inoue, Shinobu Miwa, Abhinav Bhatele, “Evaluating the Impact of Energy Efficient Networks on HPC Workloads,” 26th IEEE International Conference on High Performance Computing, Data, and Analytics, Dec. 2019.

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Koji Inoue, Akira Fujimaki, “Demonstration of a Throughput-Oriented Bit-Parallel Gate-Level Pipelined Multiplier up to 51 GHz,” IEEE International Superconductive Electronics Conference (ISEC), Sep. 2019.

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Koji Inoue, Akira Fujimaki, “Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic,” International Superconductive Electronics Conference (ISEC), July 2019.

Sandeep Kumar, Diksha Moolchandani, Takatsugu Ono and Smruti Sarangi, “F-LaaS: A Control-Flow-Attack Immune License-as-a-Service Model,” IEEE International Conference on Services Computing, pp.80-89, July 2019.

Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, Akira Fujimaki, “A 48GHz 5.6mW gate-level-pipelined multiplier using single-flux quantum logic,” IEEE International Solid-State Circuits Conference (ISSCC), pp.460-462, Feb. 2019.

Takatsugu Ono, Zhe Chen and Koji Inoue, “Improving Lifetime in MLC Phase Change Memory using Slow Writes,” International Japan-Africa Conference on Electronics, Communication and Computations, pp.65-pp.68, Dec. 2018.

Yusuke Inoue, Takatsugu Ono and Koji Inoue, “Situation-Based Dynamic Frame-Rate Control for On-Line Object Tracking,” International Japan-Africa Conference on Electronics, Communication and Computations, pp.129-pp.132, Dec. 2018.

Ghadeer Almusaddar, Teruo Tanimoto, Takatsugu Ono, Smruti Sarangi, Koji Inoue, “Whitelisting Approach Using Hardware Performance Counters in IoT Microprocessors,” 4th Career Workshop for Women and Minorities in Computer Architecture, Oct. 2018.

Masamitsu Tanaka, Yuki Hatanaka, Yuichi Matsui, Ikki Nagaoka, Koki Ishida, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki, “30-GHz Operation of Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors,” Applied Superconductivity Conference, Oct. 2018. (invited)

Omar M. Saad, K. Inoue, Ahmed Shalaby, Lotf Samy, and Mohammed S. Sayed, “Autoencoder based Features Extraction for Automatic Classification of Earthquakes and Explosions,” In Proc. of the 17th IEEE/ACIS International Conference on Computer and Information Science, pp.445-450, June 2018.

Ryuichi Sakamoto, Tapasya Patki, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Daniel Ellsworth, Barry Rountree, Martin Schulz, “Analyzing Resource Trade-offs in Hardware-overprovisioned Supercomputers,” In Proc. of the 32nd International Parallel and Distributed Processing, May 2018.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, “CPCI Stack: Metric for Accurate Bottleneck Analysis on OoO Microprocessors,” In Proc. of the International Symposium on Computing and Networking, pp.166-172, Nov. 2017.

Mihiro Sonoyama, Takatsugu Ono, Osamu Muta, Haruichi Kanaya, Koji Inoue, “Wireless Spoofing-Attack PreventionUsing Radio-Propagation Characteristics,” In Proc. of the 15th IEEE International Conference on Dependable, Autonomic and Secure Computing, pp.502-510, Nov. 2017.

Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan, “Why Do Programs Have Heavy Tails?,” In Proc. of the IEEE International Symposium on Workload Characterization, pp.135-145, Oct. 2017.

Masamitsu Tanaka, Ryo Sato, Yuki Hatanaka, Yuichi Matsui, Hiroyuki Akaike, Akira Fujimaki, Koki Ishida, Takatsugu Ono, Koji Inoue, “High-Throughput Bit-Parallel Arithmetic Logic Unit Using Rapid Single-Flux-Quantum Logic,” In Proc. of the International Superconductive Electronics Conference, June 2017.

Ryuichi Sakamoto, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Tapasya Patki, Daniel Ellsworth, Barry Rountree, and Martin Schulz, “Production Hardware Overprovisioning: Real-world Performance Optimization using an Extensible Power-aware Resource Management Framework”, 31st IEEE International Parallel & Distributed Processing Symposium (IPDPS). May 2017.

Satoshi Imamura, Keitaro Oka, Yuichiro Yasui, Yuichi Inadomi, Katsuki Fujisawa, Toshio Endo, Koji Ueno, Keiichiro Fukazawa, Nozomi Hata, Yuta Kakibuka, Koji Inoue, Takatsugu Ono, “Evaluating the Impacts of Code-Level Performance Tunings on Power Efficiency,” In Proc. of the IEEE International Conference on Big Data (BigData), pp.362-369, Dec. 2016.

Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa, “Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping,” In Proc. of the 1st High Performance Graph Data Management and Processing workshop (HPGDMP), pp.17-24, Nov. 2016.

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, “Single-Flux-Quantum Cache Memory Architecture,” In Proc. of the 13th International SoC Design Conference (ISOCC), pp.106-107, Oct. 2016.

Yoshihiro Tanaka, Keitaro Oka, Takatsugu Ono, Koji Inoue, “Accuracy Analysis of Machine Learning-Based Performance Modeling for Microprocessors,” In Proc. of the 2016 Fourth International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC), pp.87-90, May 2016.

Koji Inoue, Yuichi Inadomi, and Takatsugu Ono, “Challenges in Power Constrained High Performance Computing,” Organized Session for Green HPC, Annual Meeting on Advanced Computing System and Infrastructure, Jan. 2016.

Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi, “Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing,” In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC), No.78, pp.78:1-78:12, Nov. 2015.

Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, and Koji Inoue, “A flexible hardware barrier mechanism for many-core processors,” In Proceedings of the 2015 Asia and South Pacific Design Automation Conference (ASP-DAC), pp.61-68, Jan. 2015.

James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, and Mohammed S Sayed, “Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity,” IEEE Embedded Systems Letters, Aug. 2024.

Obed M Mogaka, Rami Zewail, Koji Inoue, and Mohammed S Sayed, “TinyEmergencyNet: a hardware-friendly ultra-lightweight deep learning model for aerial scene image classification,” Journal of Real-Time Image Processing, Vol. 21, Article Num. 51, Mar. 2024.

James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, and Mohammed S Sayed, “Performance evaluation of all intra Kvazaar and x265 HEVC encoders on embedded system Nvidia Jetson platform,” Journal of Real-Time Image Processing, Vol. 21, Article No. 67, Apr. 2024.

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, and Hiroshi Nakamura, “Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines,” IEEE Computer Architecture Letters (Early Access), Oct. 2023.

Kuan Yi Ng, Aalaa M. A. Babai, Teruo Tanimoto, Satoshi Kawakami, and Koji Inoue, “Empirical Power-Performance Analysis of Layer-wise CNN Inference on Single Board Computers,” Journal of Information Processing, July 2023.

Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, and Akira Fujimaki, “50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic with Frequency-Increased Clock Distribution,” IEEE Transactions on Applied Superconductivity, Vol. 33, Issue 4, 10 pages, June 2023.

Ikki Nagaoka, Ryota Kashima, Koki Ishida, Masamitsu Tanaka, Taro Yamashita, Takatsugu Ono, Koji Inoue, and Akira Fujimaki, “A High-Throughput Multiply-Accumulate Unit with Long Feedback Loop Using Low-Voltage Rapid Single-Flux Quantum Circuits,” IEEE Transactions on Applied Superconductivity, Vol. 33, Issue 3, 8 pages, Apr. 2023.

Tomohiro Fujii, and Masao Hirokawa, “Concealing-Restoring System for Physical Layer Data: Based on Stochastic Filtering Theory,” Physical Communication, Vol.52, pp.101602-1-101602-21. June 2022.

Emad Badry, Koji Inoue, and Mohammed Sharaf Sayed, “Fast Screen Content Coding in HEVC Using Machine Learning,” IEEE Access, Vol.9, pp.154659-154666, Nov. 2021.

Ikki Nagaoka, Koki Ishida, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, and Akira Fujimaki, “Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic,” IEEE Transactions on Applied Superconductivity, Vol.31, No.5, pp.1101405 (1)-(5), Aug. 2021.

Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kousuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, and Koji Inoue, “Superconductor Computing for Neural Networks,“ in IEEE Micro (IEEE’s Top Picks), pp.1–8, May/June 2021.

Masao Hirokawa, “Schrödinger-Cat-Like States with Dressed Photons in Renormalized Adiabatic Approximation for Generalized Quantum Rabi Hamiltonian with Quadratic Interaction,” Physics Open, Vol.5, 100039(12pages), Dec. 2020.

Emad Badry, Koji Inoue, and Mohammed Sharaf Sayed, “Decision Tree Models and Early Splitting Termination in Screen Content Extension of High Efficiency Video Coding,” IEEE Access, Vol.8, pp.143437-143452, Aug. 2020.

Kenichi Kitayama, Masaya Notomi, Makoto Naruse, Koji Inoue, Satoshi Kawakami, Atsushi Uchida, “Novel frontier of photonics for data processing – Photonic accelerator -,” APL Photonics, Vol.4, No.9, pp.090901-1-090901-24, Sep. 2019.

Abdelhay Ali, Koji Inoue, Ahmed Shalaby, Mohammed S. Sayed, Sabah Mohamed Ahmed, “Efficient Autoencoder-Based Human Body Communication Transceiver for WBAN,” IEEE Access, Vol.7 pp.117196-117205, Aug. 2019.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, ”Critical Path based Microarchitectural Bottleneck Analysis for Out-of-Order Execution,” IEICE, Vol.E102-A, No.6, pp.758-766, June 2019.

Mihiro Sonoyama, Takatsugu Ono, Haruichi Kanaya, Osamu Muta, Smruti Sarangi, Koji Inoue, “Radio Propagation Characteristics-Based Spoofing Attack Prevention on Wireless Connected Devices,” Journal of Information Processing, Vol.27, pp.322-334, Jan. 2019.

Satoshi Kawakami, Takatsugu Ono, Toshiyuki Ohtsuka, Koji Inoue, “Parallel Precomputation with Input Value Prediction for Model Predictive Control Systems,” IEICE Transactions on Information and Systems, Vol.E101-D, No.12, pp.2864-2877, Dec. 2018.

Yusuke Inoue, Takatsugu Ono, Koji Inoue, “Real-time Frame-Rate Control for Energy-Efficient On-Line Object Tracking,” IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E101-A, No.12, pp.2297-2307, Dec. 2018.

Omar M. Saad, Koji Inoue, Ahmed Shalaby, “Automatic Arrival Time Detection for Earthquakes Based on Stacked Denoising Autoencoder,” IEEE Geoscience and Remote Sensing Letters, Vol.15, Issue 11, pp.1687-1691, Nov. 2018.

Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa, “Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs,” IEICE Transactions on Information and Systems, Vol.E101-D, No.9, pp.2247-2257, Sep. 2018.

Susumu Mashimo, Ryota Shioya, Koji Inoue, “VMOR: Microarchitectural Support for Operand Access in an Interpreter,” IEEE Computer Architecture Letters, Vol.17, No.2, pp.217-220, Aug. 2018.

Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, and Masaya Notomi, “An Integrated Nanophotonic Parallel Adder,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 14, Issue 2, Article No. 26, pp.26:1-26:20, July 2018.

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, “Towards Ultra High-Speed Cryogenic Single-Flux-Quantum Computing,” IEICE Transactions on Electronics (invited paper), Vol.E101-C, No.5,pp.359-369, May 2018.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, “Dependence Graph Model for Accurate Critical PathAnalysis on Out-of-Order Processors,” Journal of Information Processing, Vol.25, pp.983-992, Dec. 2017.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki, “Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors,” IEEE Computer Architecture Letters, Vol. PP, No 99, pp.1-1, Mar. 2017.

Takayoshi Ishimoto, Yuichi Inadomi, Hiroaki Honda, Michihisa Koyama, “Parallel Performance Analysis for Electronic Structure Calculation of Metal Nanoparticles,” Journal of Computer Chemistry, Japan, vol. 14, no. 3, pp.52-53, 2015.

Koji Inoue, “How Can SFQ Technology Contribute to Quantum Computing?,” 22nd International Forum on Multicore and Multiprocessor SoCs (MPSoC), July 2024.

Koji Inoue, “Architectural Challenge for Cryogenic Superconductor Computing,” 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr. 2024.

Koji Inoue and Haruichi Kanaya, “Human resource development for Semiconductor Technologies in Fukuoka,” U.S.-Japan Collaborative Workshop: Accelerating IC Design [Phase I], Dec. 2023.

Koji Inoue, “Toward Edge-Cloud Energy Efficient AI Accelerations,” 21st International Forum on Multicore and Multiprocessor SoCs (MPSoC), June 2023.

Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, and Teruo Tanimoto, “Circuit designs for practical-scale fault-tolerant quantum computing,” IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp.1-2, June 2023.

Koji Inoue, “Next Generation Cryogenic Superconductor Computing ~From Classical to Quantum~,” IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), Apr. 2023.

Koji Inoue, “Ultra-High-Speed, Low-Power Superconductor Computing with Architectural Optimization,” The 11th East Asia Symposium on Superconductor Electronics (EASSE), Mar. 2023.

Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koji Inoue, and Akira Fujimaki, “Demonstration of a superconductor 8-bit microprocessor based on high-throughput single-flux-quantum logic circuits,” The 11th East Asia Symposium on Superconductor Electronics (EASSE), Mar. 2023.

Teruo Tanimoto, “Research Activities toward Larger-Scale Cryogenic Quantum Computer Systems,” 28th Asia and South Pacific Design Automation Conference (ASP-DAC): Designers’ Forum, Jan. 2023.

Koji Inoue, “The Road to Superconductor Computing with SFQ Devices,” Workshop on Superconducting Digital Computing Architecture Research (SGAR) in conjunction with ISCA 2022, June 2022.

Koji Inoue, “Exploring Next Generation Computing Platform: from Edge to Cloud,” 20th International Forum on Multicore and Multiprocessor SoCs (MPSoC), June 2022.

Koji Inoue, “Towards Extremely High-Speed, Low-Power Cryogenic Superconductor Computing,” Center for Research into Novel Computing Hierarchies (CRNCH) Summit, Feb. 2022.

Koji Inoue, “My-IoT: Edge-Centric IoT Platform for Cross-Industry Collaboration,” The 5th International Conference on Software Engineering and Information Management (ICSIM), Jan. 2022 .

Koji Inoue, “Ultra-Fast, Low-Power Neural Network Computing with Superconductor Devices,” JSPS-NTU Joint Seminar on Brain-Inspired Computing: Physics, Architectures, Materials, and Applications, Dec. 2021.

Masao Hirokawa, “Can We Make the Noise Filtering Theory for NISQ Computer?,” 3rd Workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems, Nov. 2021.

Satoshi Kawakami, “Towards noise-driven computing,” The Superconducting SFQ VLSI Workshop (SSV), pp.6, Nov. 2021.

Koji Inoue, “Microarchitecture Research ~ the View from Japan ~,” MICRO 2021 Panel: Microarchitecture Research: The View from the Globe, Oct. 2021 (YouTube: https://www.youtube.com/watch?v=Re4s6WZck-Q).

Koji Inoue, “Towards 100 GHz Ultra-High-Speed Superconductor Computing,” 2021 International Conference on Solid State Devices and Materials (SSDM), Sep. 2021.

Koji Inoue, “Challenges in Ultra-High-Performance Low-Power Computing towards the Post Moore Era ~A Computer Architecture Perspective~,” Asia and South Pacific Design Automation Conference (ASP-DAC), Designers Forum, Feb. 2021.

Koji Inoue and Satoshi Kawakami, “Towards Ultra-Efficient Nanophotonic AI Acceleration: from a computer architecture perspective,” Optical Fiber Communication Conference (OFC), Tu1H.1, June 2021.

Koji Inoue, “Towards Ultra-High-Speed Superconductor Computing ~Computer Architecture Perspective~,” 33rd International Symposium on Superconductivity (ISS), Dec. 2020.

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue, “How can we exploit noisy intermediate-scale quantum computers? ~A computer architecture perspective~,” Cryogenic Devices, Circuits, and Systems (QCCC), Nov. 2019.

Satoshi Kawakami, “Performance Analysis for Approximate Optical Computing – Computer Architecture Perspective -,” The International Workshop of Optical Packet Switching (OPS) and Optical Code Division Multiple Access (OCDMA), IWOO’19, Oct. 2019.

Satoshi Kawakami, “Nanophotonic Neural Network Accelerator: Challenges and Opportunities,” Asia Pacific Society for Computing and Information Technology (APSCIT), July 2019.

Koji Inoue, Satoshi Kawakami, “Challenges in Ultra-High-Performance Low-Power Nanophotonic Computing – A Computer Architecture Perspective -,” OPTICS & PHOTONICS International Congress, Apr. 2019.

Teruo Tanimoto, Takatsugu Ono, Koji Inoue, “Graph-based performance analysis on Out-of-Order processors,” The seventh Asian Workshop on Smart Sensor Systems, Mar. 2019.

Koji Inoue, Satoshi Kawakami, “Power-Performance Impact of Nanophotonic Vector-by-Matrix Multiplier,” JST Workshop: Novel frontiers of optics for computing, July 2018.

Takatsugu Ono, Yuta Kakibuka, Nikhil Jain, Abhinav Bhatele, Shinobu Miwa, Koji Inoue, “Extending A Network Simulator for Power/Performance Prediction of Large Scale Interconnection Networks,” “Modeling and Simulation of HPC Architectures and Applications held in conjunction with SIAM Conference on Parallel Processing for Scientific Computing, Mar. 2018.

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, “Logic Design of a Single-Flux-Quantum Gate-Level-Pipelined Microprocessor,” Superconducting SFQ VLSI Workshop, Invited talk, pp.6-12, Feb. 2017.

Masamitsu Tanaka, Ryo Sato, Yuki Hatanaka, Yuki Ando, Takahiro Kawaguchi, Koki Ishida, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi, Takatsugu Ono, Koji Inoue, “Energy-Efficient, High-Performance Microprocessors Based on Single-Flux-Quantum Logic,” 29th International Symposium on Superconductivity, Invited talk, Dec. 2016.

Koji Inoue, “Manycore Execution of Model Predictive Control,” The Fifth International Conference on Continuous Optimization, Invited talk, Aug. 2016.

Koji Inoue, “Impact of Manufacturing Variability in Power Constrained Supercomputing,” International Forum on MPSoC for Software-defined Hardware, Invited talk, July 2016.

Koji Inoue, “NsimPower: Interconnect Simulator for Power and Performance Prediction,” International Forum on MPSoC for Software-defined Hardware, Invited talk, July 2015.

Koji Inoue, “Towards Emerging Device Computing,” ACM SIGARCH, Computer Architecture Today, Aug. 2022 (https://www.sigarch.org/towards-emerging-device-computing/).

Koji Inoue, Jangwoo Kim, and Masamitsu Tanaka, “How did the road to new adventure in Superconductor Neural Network Accelerator happen?,” IEEE TCCA Blog, Nov. 2021 (http://www.blog.ieeetcca.org/how-did-the-road-to-new-adventure-in-superconductor-neural-network-accelerator-happen/).

Teruo Tanimoto, “APSCIT Computer Science and Informatics Research Contribution Award” (2019)

Satoshi Kawakami, Asia Pacific Society, “Award for outstanding research achievement” (2019)

Mihiro Sonoyama, “2017 Excellent Student Award of The IEEE Fukuoka Section” (2018)

Masamitsu Tanaka, Ryo Sato, Yuki Hatanaka, Yuichi Matsui, Hiroyuki Akaike, Akira Fujimaki, Koki Ishida, Takatsugu Ono, Koji Inoue, “Design Contest Award Honorable Mention, The 23rd International Symposium on Low Power Electronics and Design (ISLPED)” 2017.

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, and Hiroshi Nakamura, “SFQ counter-based precomputation for large-scale cryogenic VQE machines,” Work-in-progress poster session, The 61st Design Automation Conference, June 2024.

Kuan Yi Ng, Takeshi Nanri, Teruo Tanimoto, Satoshi Kawakami, and Koji Inoue, “Analyzing Carbon Footprint Implications of Hardware Replacement: Preliminary Evaluation Targeting CPUs in Supercomputer Systems,” 2023-ARC-255(13), pp.1-8, Dec. 2023.

Pratiksha Mundhe, Kosuke Hiwaki, Masamitsu Tanaka, and Koji Inoue, “Detection of timing errors in SFQ circuits (poster),” The Joint Workshop of 5th Workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems (QCCC 2023), 16th Superconducting SFQ VLSI Workshop (SSV 2023), and 2nd International Workshop of Spin/Quantum Materials and Devices (IWSQMD 2023), Nov. 2023.

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, and Hiroshi Nakamura, “Toward system-level optimization of superconducting quantum computers: The case of QAOA,” The Joint Workshop of 5th Workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems (QCCC 2023), 16th Superconducting SFQ VLSI Workshop (SSV 2023), and 2nd International Workshop of Spin/Quantum Materials and Devices (IWSQMD 2023), Nov. 2023.

Zhengpan Fei and Koji Inoue, “Preliminary Data-Pattern Analysis towards Energy-Efficient Adaptive In-Cache Computing for CNN Accelerations,” No. ICD-259, Vol. 123, pp. 70-75, Nov. 2023.

Kuan Yi Ng and Koji Inoue, “A Preliminary Case Study on Hardware Upgrade Cycle and Carbon Emissions of Supercomputer,” ACM Student Research Competition (SRC), Oct. 2023.

Aalaa M.A. Babai and Koji Inoue, “Quantifying Performance Opportunities of Novel Non-volatile FPGAs for Accelerating Energy-Constrained Intelligent IoT,” ACM Student Research Competition (SRC), Oct. 2023.

Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatugu Ono, Koji Inoue, and Akira Fujimaki, “Gate-level-pipeline SFQ circuits for high-throughput floating-point arithmetic,” Proceedings of the European Conference on Applied Superconductivity (EUCAS), Sep. 2023.

Tesshu Nakamura, Makoto Miyamura, Koji Inoue, Satoshi Kawakami, Toshitsugu Sakamoto, Munehiro Tada, and Teruo Tanimoto, “Dynamically Reconfigurable Decoder Architecture for Adaptive Error Correction Using Cryogenic Non-Volatile FPGAs,” Workshop and Tutorial: I too can Quantum! (I2Q), June 2023.

Takumi Inaba, Takatsugu Ono, Koji Inoue, and Satoshi Kawakami, “Evaluating floating-point multipliers with opto-electrical hybrid circuits,” ACM International Conference on Computing Frontiers, Poster, May 2023.

Aalaa M.A. Babai and Koji Inoue, “Get your Accelerator ASAP: Almost Application Specific Accelerators Paths,” ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Wild and Crazy Ideas (WACI) Session, Mar. 2023.

Masamitsu Tanaka, Ikki Nagaoka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Koji Inoue, and Akira Fujimaki, “High-throughput single-flux-quantum circuits based on gate-level-pipelining toward artificial intelligence applications,” 15th Superconducting SFQ VLSI Workshop (SSV) / 4rd Workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems (QCCC), Sep. 2022.

Kuan Yi Ng, Aalaa M.A. Babai, Satoshi Kawakami, Teruo Tanimoto, and Koji Inoue, “Layer-wise power/performance modelling for single-board CNN inference,” SIG Technical Reports, Vol.2022-ARC-248 No.13, pp.1-11, Mar. 2022.

Ikki Nagaoka, Koki Ishida, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, and Akira Fujimaki, “Demonstration of a 52-GHz, energy-efficient, bit-parallel multiplier using low-voltage rapid single-flux-quantum logic,” 2020 Applied Superconductivity Conference (ASC), Nov. 2020.

Ikki Nagaoka, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Koji Inoue, Akira Fujimaki, “High-throughput gate-level-pipelined SFQ multipliers,” 13th Superconducting SFQ VLSI Workshop (SSV), Jan. 2020.

Masamitsu Tanaka, Ikki Nagaoka, Koki Ishida, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki, “Development of Gate-Level-Pipelined SFQ Circuits toward Ultra-High-Speed Cryogenic Computing,” 13th Superconducting SFQ VLSI Workshop (SSV), Jan. 2020.

Masamitsu Tanaka, Ikki Nagaoka, Kyosuke Sano, Taro Yamashita, Koki Ishida, Takatsugu Ono, Koji Inoue, Akira Fujimaki, “Development of 50-GHz, High-Throughput Rapid Single-Flux-Quantum Circuits toward Ultra-Fast, Energy-Efficient Computing,” 10th ACASC/2nd Asian-ICMC/CSSJ Joint Conference, Jan. 2020.

Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue, “Prototype Design of 32 GHz Microprocessor based on Superconducting Single-Flux-Quantum Logic,” The International Conference for High Performance Computing (SC), Nov. 2019.

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, “Prototype Design of 31 GHz Single-Flux-Quantum Gate-Level-Pipelined Microprocessor,” 12th Superconducting SFQ VLSI Workshop (SSV), Jan. 2019.

Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue, “Prototype Design of 30 GHz Superconducting Single-Flux-Quantum Microprocessor Towards Cryogenic General Purpose Computing,” The 52nd International Symposium on Microarchitecture, Student Research Competition, Oct. 2018.

Tatsuya Hoshino, Koji Inoue, “Time-Domain Neural Network with Superconducting Single-Flux-Quantum Devices,” The 52nd International Symposium on Microarchitecture, Student Research Competition, Oct. 2018.

Ghadeer Almusaddar, Teruo Tanimoto, Takatsugu Ono, Smruti Sarangi, Koji Inoue, “Whitelisting Approach Using Hardware Performance Counters in IoT Microprocessors,” 4th Career Workshop for Women and Minorities in Computer Architecture, Oct. 2018.

Takatsugu Ono, “Hardware-based malware detection for IoT microprocessors,” The 6th International Workshop on Cyber Security-Workshop on IoT Security : Secure Smart Homes, Sep. 2018.

Ghadeer Almusaddar, Takatsugu Ono, Smruti Sarangi, Koji Inoue, “Whitelisting Approach Using Hardware Performance Counters in IoT Microprocessors,” IEICE Tech. Rep., Vol. 118, No. 3, HWS2018-6, pp. 29-34, Apr. 2018.

Takatsugu Ono, “Secure Computing Platform for IoT Devices,” The 6th International Cybersecurity Workshop, Jan. 2018.

Takatsugu Ono, “Protecting an IoT Device from Malware – A Processor Architecture Perspective,” Workshop on Architectural Implications of Security in IoT Processors, Nov. 2017.

Yuta Kakibuka, Yuichiro Yasui, Takatsugu Ono, Katsuki Fujisawa, Koji Inoue, “Performance evaluation of Graph500 considering CPU-DRAMpower shifting,” Poster session The International Conference for High Performance Computing, Networking, Storage, and Analysis, Nov. 2017.

Takatsugu Ono, “Developing an Interconnection Network Simulator for Energy Efficient Large Scale Networks,” Workshop on Recent Topics in High Performance Computing, Sep. 2017.

Yusuke Inoue, Takatsugu Ono, Koji Inoue, “Adaptive Frame-Rate Optimization for Low Energy Object Tracking,” Work-in-Progress session at the 2016 Design Automation Conference (DAC), June 2016.

Keitaro Oka, Wenhao Jia, Margaret Martonosi, and Koji Inoue, “Characterization and Cross-Platform Analysis of High-Throughput Accelerators,” In Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) as a poster abstract, Mar. 2015.